1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a structure of a data I/O (input/output) portion of a synchronous semiconductor memory device which operates in synchronization with an external clock signal.
2. Description of the Background Art
As a result of increase in operation speed of microprocessors (which will be referred to as xe2x80x9cMPUsxe2x80x9d hereinafter) in recent years, fast access to DRAM (Dynamic Random Access Memory) used as main storage devices has been desired or demanded. For meeting such demands, synchronous DRAMs (which will be referred to as xe2x80x9cSDRAMsxe2x80x9d hereinafter) or the like operating in synchronization with clock signals have been used.
The internal operation of the SDRAM or the like is divided into a row-related operation and a column-related operation for control.
For allowing further fast operations, the SDRAM has employed a bank structure, in which a memory cell array is divided into banks operating independently of each other. In this structure, the operation of each bank is divided into a row-related operation and a column-related operation which are controlled independently of each other.
However, some of present systems require further fast operations of the semiconductor memory devices.
Meanwhile, some of other systems do not require such fast operations. Accordingly, in view of power consumption or the like, it is not desirable to use the above SDRAM, which is designed for the system requiring the maximum operation speed, for the system allowing a lower operation frequency without changing the specifications for the fastest operation.
In some systems, the synchronous operation of the whole system is performed in such a manner (unidirectional manner) that a reference clock signal for synchronous operation is issued only from a controller side. Another manner (bidirectional manner) may also be employed, in which case synchronous clock signals are equally distributed to a control device and a semiconductor memory device forming the system.
Accordingly, it may be necessary to change the operation mode of the SDRAM itself for the faster operations in the above two cases in view of an influence of skew in clock signals and others.
For the above change, different designs may be employed for the specific purposes, respectively. However, this increases cost for such designs and manufacturing.
As already described, increase in throughput of the DRAM is a major factor in improving the performance of system. For this reason, the SDRAM which performs input/output of data in synchronization with an externally supplied clock has become mainstream instead of an EDO type which is the previous mainstream of DRAMs.
In this SDRAM type, data, addresses and various commands are supplied to a chip in synchronization with rising edges of the externally supplied clock. Also, internal processing of the memory chip is partially performed in synchronization with the clock, and output is performed in synchronization with edges of the external clock.
However, it has been pointed out that further higher throughput is required in systems used for handling data such as image data at a high speed.
As a new input/output method of the DRAM for the above purpose, a double-data-rate synchronous DRAM, which will be referred to as a xe2x80x9cDDR-SDRAMxe2x80x9d hereinafter, has been proposed. The DDR-SDRAM is externally supplied with a strobe clock for data, and takes in the data in synchronization with both the rising and falling edges. Further, it internally produces and sends a strobe clock in synchronization with the data output.
A kind of DDR-SDRAM is shown in a block diagram of FIG. 48. FIG. 48 shows data input/output through only one data I/O terminal.
In a data write operation, data which is supplied from a pad 9000 in synchronization with a strobe clock is sent through an input buffer to an input register, and is temporarily held therein. In this operation, data supplied at the time of rising of the clock and data supplied at the time of falling of the clock are held in different input registers 9002 and 9003.
Depending on even and odd addresses, an input control circuit changes a connection in a connection switch 9004 between the data bus and registers.
After a latency of a data strobe clock, the data is issued onto an internal data bus in synchronization with the clock. The latency of data strobe is usually equal to two clocks. A memory array is divided in accordance with the even and odd addresses, and the divided portions receive data from the corresponding data buses for storing the data in the corresponding memory cells, respectively. In the operation of continuously writing the data, address counters 9006 and 9007 issue required addresses to the memory arrays.
In this operation, address counters 9006 and 9007 issue different patterns depending on whether the corresponding memory array is assigned even addresses or odd addresses.
A data read operation is performed in accordance with the addresses sent to the memory array from address counters 9006 and 9007, and data is read from the corresponding memory cells onto the data bus.
An output control circuit 9008 changes the connection between the data bus and output registers depending on whether the address is even or odd, and thereby stores the data in the corresponding register. In accordance with the latency already set, the output control circuit changes a state of a switch 1012 on the output side for alternately issuing the data latched in output registers 9009 and 9010 in synchronization with the rising and falling edges of the clock.
According to the above system, it is necessary to prepare different chips for the SDRAM of the single data rate type (which will be referred to as the xe2x80x9cSDR-SDRAMxe2x80x9d hereinafter) and the DDR-SDRAM due to difference in output method, although many similarities exist between chip internal operations of these SDRAMs.
In the operation mode of the DDR-SDRAM described above, the data which was written is externally read in the immediately subsequent read operation in some cases. In this case, an efficiency of data output is low if the operation is performed such that the data which was once written into the memory cell array is read out by accessing the memory cell in accordance with the externally supplied address signal.
An object of the invention is to provide a synchronous semiconductor memory device, which allows flexible control of a margin in chip operation with respect to an external clock signal in accordance with requirements by a system.
Another object of the invention is to provide a synchronous semiconductor memory device, which can selectively achieve a single-data-rate SDRAM and a double-data-rate SDRAM on the same chip.
Yet another object of the invention is to provide a synchronous semiconductor memory device, which can reduce a time required between data writing and subsequent data reading, and can increase an operation efficiency without requiring increase in chip area.
In summary, the invention provides a synchronous semiconductor memory device for receiving an address signal and a control signal in synchronization with an external clock signal, including a memory cell array, a first internal synchronous signal generating circuit, a second internal synchronous signal generating circuit, a control signal input circuit, a memory cell select circuit, a plurality of data I/O nodes, an interface circuit, a gate circuit and a write timing control circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns. The first internal synchronous signal generating circuit generates a first internal clock signal synchronized with the external clock signal and having a higher frequency than the external clock signal. The second internal synchronous signal generating circuit generates a second internal clock signal synchronized with the external clock signal.
The control signal input circuit takes in the address signal and the control signal in synchronization with the second internal clock signal. The memory cell select circuit selects the memory cell in accordance with the address signal. The plurality of data I/O nodes are supplied with write data to be written into the memory cells.
The interface circuit is arranged between the memory cells selected by the memory cell select circuit and the data I/O nodes, and the receives the write data. The interface circuit includes a data I/O circuit for receiving the write data from each of the plurality of data I/O nodes in synchronization with the second internal clock signal in a first operation mode, and receiving the write data from each of the plurality of data I/O nodes in synchronization with the first internal clock signal in a second operation mode.
The gate circuit selectively applies the write data to a selected memory cell column. The writing timing control circuit changes timing for activating the gate circuit after the control signal instructs the write operation, depending on whether the operation is in the first operation mode or the second operation mode.
According to another aspect of the invention, a synchronous semiconductor memory device for receiving an address signal and a control signal in synchronization with an external clock signal, includes a control circuit, a memory cell array, a first internal synchronous signal generating circuit, a control signal input circuit, a memory cell select circuit, a plurality of data I/O nodes and a plurality of interface circuits.
The control circuit controls an operation of the synchronous semiconductor memory device. The memory cell array has a plurality of memory cells arranged in rows and columns.
The first internal synchronous signal generating circuit generates a first internal clock signal synchronized with the external clock signal. The control signal input circuit takes in the address signal and the control signal. The memory cell select circuit selects the memory cell in accordance with the address signal. The plurality of data I/O nodes are supplied with data for transmission to and from the memory cells.
The plurality of interface circuits are arranged between the memory cells selected by the select circuit and the data I/O nodes for transmitting the write data, respectively.
Each of the interface circuits includes a first latch circuit, a second latch circuit and a transfer circuit.
The first latch circuit is controlled by the control circuit to receive and hold, in synchronization with the first internal clock signal, the plurality of data supplied in time series to the corresponding I/O node, and to send the held data to the selected memory cells as parallel data.
The second latch circuit is controlled by the control circuit to receive and hold the plurality of data read out from the selected memory cells, and to convert the held data into time-series data in synchronization with the first internal clock signal for applying the time-series data to the corresponding I/O node.
The transfer circuit is controlled in the write operation by the control circuit for transferring the data held in the first latch circuit to the second latch circuit.
The control circuit converts the data transferred to and held in the second latch circuit into time-series data in synchronization with the first internal clock signal, and applies the time-series data to the corresponding I/O node when the control circuit receives an instruction for the read operation and a read address matching with an address applied in the immediately preceding read operation or the immediately preceding write operation.
According to still another aspect of the invention, a synchronous semiconductor memory device for receiving an address signal and a control signal based on mutually complementary first and second external clock signals includes a memory cell array, a control circuit, a memory cell select circuit, a plurality of data I/O nodes and an interface circuit.
The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cell array includes a plurality of memory cell blocks.
The control circuit controls an operation of the synchronous semiconductor memory device in synchronization with the first and second external clock signals.
The memory cell select circuit is provided correspondingly to each of the memory cell blocks for selecting the plurality of memory cells at a time in accordance with the address signal. The plurality of data I/O nodes are supplied with read data from the memory cells.
The interface circuit is arranged between the memory cells selected by the memory cell select circuit and the data I/O nodes for transmitting the read data.
The interface circuit includes a plurality of holding circuit pairs and a data I/O circuit.
The plurality of holding circuit pairs are provided correspondingly to the pairs of the memory cell blocks, respectively, and hold the read data read from the plurality of memory cells.
The data I/O circuit applies the read data held in the holding circuit pairs alternatively to the corresponding data I/O nodes in synchronization with the activation edges of the first and second external clock signals in a first operation mode, and applies the read data held in one of the paired holding circuits to the corresponding data I/O node in synchronization with one of the first and second external clock signals in a second operation mode.
Accordingly, a major advantage of the invention is that a margin in the write operation can be adjusted flexibly in accordance with specifications of a system.
Another advantage of the invention is that the interface circuit operates as a cache memory, and therefore fast reading can be performed without requiring increase in chip area.
Still another advantage of the invention is that a latency or a waiting time before start of the read operation can be reduced even when the read operation is to be performed immediately after the write operation.